IBM Loon: 2 Logical Qubits — First Step on the Fault-Tolerant Roadmap

IBM announced the Loon processor (2025) as the opening milestone of its fault-tolerant roadmap: 2 logical qubits encoded in ~100 physical qubits using a compact code inspired by qLDPC (gross code) architecture, targeting the path to 200 LQ by 2029.

In June 2025, IBM revealed an updated fault-tolerant quantum roadmap with the Loon processor as its first hardware milestone. Loon encodes 2 logical qubits from approximately 100 physical qubits using a compact error-correction code with hardware requirements similar to IBM's gross code (bivariate bicycle / qLDPC), though smaller in scale.

Key technical highlights of Loon:

2 LQ from ~100 physical qubits — compact code, not full gross code
Six-way coupler: a central qubit connected via tunable couplers to 6 neighboring qubits, demonstrating low crosstalk and high fidelity
C-couplers up to 16–20 mm in length for non-local qubit connectivity, maintaining low error rates and coherence times of several hundred microseconds
Real-time decoder testing for the future gross code implementation

Loon is the foundation of IBM's modular fault-tolerant architecture that progresses through Kookaburra (2026, 1 gross code block), Cockatoo (2027, 24 LQ), Starling (2028, ~200 LQ test), and the large-scale fault-tolerant Starling (2029, ~200 LQ / 100 million gates). IBM's gross code encodes 12 logical qubits per block from 288 physical qubits — roughly one-tenth the overhead of surface code — enabling practical scaling toward fault tolerance.